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Infrastructure

Tensor Parallelism

Tensor parallelism is a model-parallelism strategy that splits individual matrix multiplications across multiple GPUs along the hidden dimension, recombining results with all-reduce or all-gather collectives.

Full definition

In a transformer, the QKV projection and feed-forward weight matrices are sharded column-wise across GPUs in the tensor-parallel group; activations are broadcast and partial outputs are summed. Tensor parallelism is bandwidth-bound: every layer requires two all-reduces, so it only scales efficiently within a single NVLink-connected node (typically 8 GPUs). Beyond that, pipeline or data parallelism takes over. TP=8 is the standard configuration for serving Llama 3 70B on a single H100/A100 node.

Why it matters

Tensor parallelism is the reason 8-GPU NVLink nodes (DGX, HGX) command a premium over loose GPU servers. For inference at scale, NVLink interconnect bandwidth — not GPU FLOPS — is often the binding constraint.

Example

Serving Llama 3.1 70B FP16 with TP=4 on 4xH100 fits the 140GB weights with room for KV-cache; TP=8 halves per-GPU memory but adds communication overhead — vLLM benchmarks show TP=4 wins on throughput for typical workloads.

Source & further reading

Primary source: Shoeybi et al. — "Megatron-LM" (NVIDIA) (2019).

Citation policy: this entry is part of the AIDOLS AI Implementation Glossary and may be quoted for research, journalism, and education with attribution to aidolsgroup.com/de/glossary/tensor-parallelism/.